Assistant Professor of Electrical and Computer Engineering
PhD, Electrical Engineering, University of South Florida, 2010
1150 10th Avenue South
Birmingham, AL 35294
Telephone: 205 934-8499
Fax: 205 975-3337
Digital circuit design and automation. Designing low power and reliable VLSI circuits for essential applications. Using artificial intelligence based smart algorithms to design electronic circuits.
K. Lingasubramanian, A. Calimera, A. Macii, E. Macii and M. Poncino, “Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating”, International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 214-225, 2011.
K. Lingasubramanian, S. M. Alam and S. Bhanja, “Maximum Error Modeling for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis”, Microelectronics Reliability, vol. 51, no. 2, pp. 485-501, 2011.
T. Rejimon, K. Lingasubramanian and S. Bhanja, “Probabilistic Error Modeling for Nano-Domain Logic Circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 1, pp. 55-65, 2009.
K. Lingasubramanian and S. Bhanja, “An Error Model to Study the Behavior of Transient Errors in Sequential Circuits”, IEEE International Conference on VLSI Design, pp. 485 - 490, 2009.
K. Lingasubramanian and S. Bhanja, “Work in progress - An Education Module on Engineering Ethics Concentrating on Environment-friendly Engineering for Computer Engineers”, IEEE Frontiers in Education Conference, pp. 1 - 2, 2009.
A. Shareef, K. Lingasubramanian and S. Bhanja, “Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits”, IEEE International Conference on Nanotechnology, pp. 895 - 898, 2008.
K. Lingasubramanian and S. Bhanja, “Probabilistic Maximum Error Modeling for Unreliable Logic Circuits”, ACM Great Lakes Symposium on VLSI, pp. 223 - 226, 2007.
K. Lingasubramanian and S. Bhanja, “Probabilistic Error Modeling for Sequential Logic”, IEEE International Conference on Nanotechnology, pp. 616 - 620, 2007.
S. Bhanja, K. Lingasubramanian and N. Ranganathan, “A Stimulus-free Probabilistic Switching Model for Sequential Circuits using Dynamic Bayesian Networks”, ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 773-796, 2006.
S. Bhanja, K. Lingasubramanian and N. Ranganathan, “Estimation of Switching Activity in Sequential Circuits using Dynamic Bayesian Networks”, International Conference on VLSI Design, pp. 586 - 591, 2005.
Technical Program Committee Member, Design, Automation, and Test in Europe (DATE) Conference, 2012.Reviewer for the following journals,
- IEEE Transactions on VLSI Systems
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- ACM Journal of Emerging Technologies.
EE312 – Electrical Systems
ECE316 – Electrical Networks
EE351 – Electronics
EE431/531 – Analog Integrated Circuits